1. Field of the Invention
This invention relates to electrostatic discharge protection for electronic devices comprising an array of pixels. The invention particularly relates to an electrostatic discharge protection circuit suitable to a display device that is used in an apparatus requiring a low power consumption and to a display device taking such protection measures.
2. Description of the Related Art
Electrostatic discharge (ESD) damage is a well known phenomenon which can occur during the fabrication of semiconductor devices, such as metal-oxide semiconductor (MOS) structures. In particular, ESD damage can result in gate insulating layer breakdown, large shifts in threshold voltages and large leakage currents between transistor electrodes.
ESD damage has been found to be a particular problem during the fabrication of devices using arrays of thin film transistors (TFTs), such as those serving as pixel switching elements in pixellated devices. Arrays of these transistors are used in, for example, active matrix liquid crystal displays and other active matrix display devices, and in sensing array devices such as radiation imaging detectors as well. During fabrication, significant quantities of charge may form on the source and drain electrodes of the TFTs. In particular, the row and column conductors used to address the individual pixels in the array provide long conductors on which static charge can be picked up and subsequently transferred to the TFT electrodes.
This static charge may result in breakdown of the gate insulating layer, and can result in a voltage differential between the gate and source electrodes or the gate and drain electrodes which can in turn cause the threshold voltage of the TFTs to shift.
The problem of ESD damage is not confined to TFT array devices but can be found also in array devices using alternative kinds of switching elements, for example two terminal devices such as thin film diodes or other non-linear devices.
The need to prevent ESD damage is widely recognised, and several different approaches have been developed. One example is the use of shorting bars surrounding the TFT array which link all of the source lines and gate lines of the individual TFTs together. The shorting lines are manufactured at the same time as the gate and source lines, so that the gate and source electrodes remain at the same potential throughout the fabrication process. This prevents any voltage differential from occurring across electrodes of the transistors, and therefore prevents ESD damage within the TFT devices.
However, the shorting lines must be removed from the device before the switching array can be used. This requires a cutting process, which introduces additional processing steps, and also means that the ESD protection is not available from that cutting process until of connecting peripheral circuitry to the TFT array.
It is also known to provide ESD damage protection circuits (surge protection circuits) which remain in place even during operation of the device from a Patent Document 1, for example.
(Patent Document 1)
Japanese Patent Application Laid-Open No. 119256/99 (*1Paragraph Nos. [0019] to [0021] and FIG. 9, and *2Paragraph Nos. [0029] to [0060] and FIG. 1)
These protection circuits typically allow charge to flow between a discharge element (reference potential line) and the row or column lines (scanning lines or signal lines) when a voltage differential is exceeded with respect to a certain reference. A problem with these protection circuits is that they may consume a considerable proportion of the total power budget of the device. For example, in low power active matrix LCD applications, more than 50% of the total display power budget may be consumed by the protection circuits. Therefore, whilst these protection circuits may provide protection during fabrication of the TFT array and also during connection of peripheral circuitry, unacceptably high levels of power consumption may result during operation of the manufactured device.
The Patent Document also discloses a way to suppress power consumption of the protection circuit itself during ordinary operation of the device by applying a predetermined voltage to the discharge elements (*2). However, the effect of suppressing power consumption is still insufficient. Especially, such display devices, for example used in portable devices requiring long time operation by a limited capacity of a battery, whose low power consumption is regarded as very important in respect of quality of the products, need even more improvement of the effect of suppressing power consumption. These types of display devices may be considered to be seriously defective in the product quality even if some ones have surface impressions that they waste very little power consumption. Therefore, we would like to reduce wasteful power consumption as much as possible.
In addition, the technique mentioned in the above document requires provision of a power supply conductive line connecting a power supply or voltage supply source to the discharge clement for applying a voltage to the discharge element. The conductive line is applied with a fixed voltage of a constant value and extends from the outer edge side of the array substrate to the discharge element at the display area side, whereby electronical corrosion is empirically supposed to be easy to occur.